1. Field of the Invention
The invention generally relates to DLL circuits, and particularly relates to a DLL circuit which generates a clock signal having a predetermined delay relative to a clock signal input from an exterior.
2. Description of the Related Art
A DLL (Delay Locked Loop) circuit serves to control the delay time of a delay element by a feedback loop, such that a delay clock signal derived by delaying an input clock signal by the delay element and the input clock signal have a predetermined delay time difference with each other.
FIG. 1 is a block diagram showing an example of the construction of a related-art DLL circuit.
A DLL circuit 10 of FIG. 1 includes a phase comparator 101, a charge pump 102, a loop filter 103, a voltage-controlled delay element (VCDL) 104, and a voltage-controlled delay element (VCDL) 105. A clock signal CLK input from an exterior is supplied to the voltage-controlled delay element 104. The voltage-controlled delay element 104 receives the output of the loop filter 103 as an input control voltage, and delays the clock signal CLK by a delay length responsive to the control voltage. As for the construction of the voltage-controlled delay element 104, provision may be made to reduce a delay length in response to a drop in the input control voltage, or may be made to reduce a delay length in response to a rise in the input control voltage. For the sake of convenience of explanation, the construction assumed here is such that the delay length is reduced in response to a drop in the input control voltage.
The delay clock signal that is output from the voltage-controlled delay element 104 is supplied to one input of the phase comparator 101. The other input of the phase comparator 101 receives the clock signal CLK input from the exterior.
The phase comparator 101 compares the timing of edges of the clock signal CLK with the timing of edges of the delay clock signal. When the timing of the clock signal CLK is earlier, the phase comparator 101 supplies a down-instruction signal to the charge pump 102. In response to the down-instruction signal, the charge pump 102 draws electric charge out of the loop filter 103, resulting in the output voltage of the loop filter 103 being lowered. Consequently, the delay time of the voltage-controlled delay element 104 is shortened.
When the timing of the clock signal CLK is later, the phase comparator 101 supplies a up-instruction signal to the charge pump 102. In response to the up-instruction signal, the charge pump 102 supplies electric charge to the loop filter 103, resulting in the output voltage of the loop filter 103 being raised. Consequently, the delay time of the voltage-controlled delay element 104 is lengthened.
Through such feedback control, the delay of the delay clock signal is adjusted in such a manner that the edges of the delay clock signal output from the voltage-controlled delay element 104 are aligned with the edges of the clock signal CLK input from the exterior. Specifically, the delay of the voltage-controlled delay element 104 is adjusted to be equal to once clock cycle of the clock signal CLK.
The voltage-controlled delay element 105 has the same circuit construction as the voltage-controlled delay element 104, and receives the same output voltage of the loop filter 103 that is supplied to the voltage-controlled delay element 104. With this provision, the voltage-controlled delay element 105 delays a data signal DATA by a delay length equal to the clock cycle of the clock signal. The delay length controlled by the DLL circuit 10 is stable regardless of the operating voltage of the DLL circuit 10 or ambient temperature. In this manner, a data path having a desired delay length is provided.
[Patent reference 1] Japanese Patent Application Publication No. 2000-163963